Daniel Hsu

Daniel Hsu has extensive experience in VLSI chip implementation with a focus on physical design. Currently serving as a Senior Manager in DFT at Ambarella Inc since July 2015, Daniel has held various titles, including Senior Staff DFT Engineer and Senior Backend Engineer, contributing to multiple aspects of design for test and design engineering. Prior to this role, Daniel worked at TSMC from August 2011 to July 2015 as a Senior Engineer in the Test-Chip Design Department, where responsibilities included RTL coding, memory BIST, and silicon to simulation correlation. Daniel began their career with an internship at GUC and a brief internship at AWB-Accton Wireless Broadband Corp. Educational achievements include a Master's Degree in Electronics Engineering from National Chiao Tung University and a Master's Degree in Embedded Systems and Industrial Informatics from Paris-Sud University. A Bachelor's Degree in Electronics Engineering from National Chiao Tung University was also obtained.