Yanshen Su is a Senior Staff ASIC Design Engineer at Ambarella Inc, where they focus on IP-level RTL design, DFT-related RTL design, and full-chip integration. Previously, Yanshen worked as an ASIC Design Engineer, contributing to the development of memory sub-systems, image signal processing pipelines, and enhancing DRAM performance for various SoCs. Yanshen holds a Master's degree in Electrical and Electronics Engineering from the Georgia Institute of Technology and a Bachelor's degree in Telecommunication Engineering from Beijing University of Posts and Telecommunications. In addition to their design expertise, Yanshen has experience in developing comprehensive verification environments and has participated in wireless communication R&D.
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