奕恩 曾

奕恩 曾 has a total of three work experiences. From 2020 to present, they worked at Ambiq as a Senior Radio Frequency Design Engineer. Prior to that, from 2019 to 2020, they were employed at Cadence Design Systems as a Lead Application Engineer. Starting from 2014, they worked at 聯發科, first as an RFIC Design Engineer from October 2014 to June 2018, and then as an RFIC Design Senior Engineer from June 2018 to March 2019. At 聯發科, they were involved in CMOS power amplifier design for 4G LTE application.

奕恩 曾 received a Bachelor's degree in Electrical, Electronics and Communications Engineering from National Chiao Tung University in 2012. Following that, they pursued a Master's degree in the same field at National Taiwan University from 2012 to 2014.