Pavan S is a skilled Physical Design Engineer with extensive experience in the semiconductor industry. Currently employed at Ampere since September 2018, Pavan previously worked at Intel Corporation from May 2012 to September 2018 as a SoC Physical Design Engineer, demonstrating expertise in Synopsys DC, ICC, and PT tools with successful implementations of multiple blocks across 10nm, 14nm, and 28nm technology nodes. Pavan also completed a Graduate Technical Internship at Intel Corporation in 2011, focusing on Random Logic Synthesis, Floor-planning, Synthesis, and Place & Route concepts. Pavan holds a Master’s degree in Electrical Engineering from Arizona State University, attained between 2010 and 2012.
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