Santosh Pathak

Santosh Pathak is a seasoned professional with over 20 years of experience in design verification within the VLSI industry. Currently serving as a Senior Verification Manager at Analog Devices, they previously held significant roles at Intel Corporation, Cadence Design Systems, and Texas Instruments, leading teams in SOC validation and verification methodologies for HPC/AI domains. Santosh earned an M.Tech in VLSI Design Tools and Technology from the Indian Institute of Technology, Delhi. Their expertise spans across various verification methods, ensuring successful silicon designs and performance validation across a wide range of ARM and Intel technologies.