Siddarth E P

Siddarth E P is a Senior Design Verification Engineer at Analog Devices, specializing in SoC verification related to audio processing, including I2S and DSP for ASIC products. With over six years of experience in VLSI design verification, Siddarth has developed expertise in programming languages like Verilog and SystemVerilog, as well as verification methodologies such as UVM. Previously, they held positions at Tessolve and Test and Verification Solutions, focusing on design engineering and verification. Siddarth graduated with a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Bapuji Institute of Engineering and Technology in 2019.