Ashok V

Ashok V is an experienced design engineer with a strong background in silicon design and RTL implementation. At AMD, Ashok held the position of Silicon Design Engineer II, focusing on the RTL implementation of video processor engine blocks and debugging pipeline functionalities. Prior to that, Ashok served as a Teaching Assistant at Texas A&M University-Kingsville, assisting in a course on Very Large-Scale Integrated Circuits. Ashok also worked as an RTL Design Engineer at ASIC Technologies Pvt Ltd, where responsibilities included designing with Verilog and working on the AMBA communication protocol. Currently, Ashok is a Design Engineer at AppLab Systems, Inc, contributing to the micro-architecture of the BHSSI bridge and managing timing constraints across various interfaces.