Caoyuan

Caoyuan Ma is a CPU Design Engineer with a solid background in computer architecture and VLSI design, focusing on RTL design, verification, and digital circuit design. They began their career as an ASIC Design Engineer Intern at Marvell Semiconductor in 2018, contributing to the development of a next-generation Fast Ethernet PHY Transceiver. Currently, Caoyuan employs their skills at Apple, working on Last Level Cache and Memory Subsystem design verification since 2019. They hold a Bachelor's degree from Peking University and a Master's degree from the University of Michigan.