Cassie Y.

Cassie Y. is a CPU microarchitect and RTL engineer with over 9 years of experience in the field. They currently design CPU backend Load-Store-Unit micro-architecture and other functional units for custom Apple A-series processors. Cassie has previously worked as a hardware engineer at GE, where they designed control systems and received the Best Teamwork Award, and as an interim engineering intern at Qualcomm, where they utilized Python and Verilog for automation and design tasks. They hold a Master's degree in Electrical Engineering from the University of Michigan, complemented by a B.S.E in Electric and Computer Engineering from Shanghai Jiao Tong University.