Chaitanya P.

Chaitanya P. possesses extensive experience in digital design and verification, having worked in various roles across leading technology firms. The career began with an internship at Zarlink Semiconductor, focusing on the design and verification of a voice control processor ASIC. Following this, Chaitanya advanced to a Senior Engineer position at Link-A-Media Devices, specializing in digital design verification of HDD and SSD controller SOCs. A significant tenure at Apple included roles as an ASIC Design Engineer from III to V, where responsibilities encompassed LPDDR4 PHY and memory controller verification, combined with a prior position at Oracle Corporation as a Senior Hardware Design Engineer focused on the functional verification of coherency subsystems for next-generation volume servers. Academic credentials include a Master of Science in Electrical Engineering from Texas A&M University and a Bachelor of Technology in Electronics and Communication Engineering from the National Institute of Technology Warangal.