Harish Patel

Harish Patel is an experienced professional in the field of design verification, currently serving as a Cellular SoC DV at Apple since December 2020. Prior to this role, Harish held positions as a Sr Principal DV Architect at Tachyum and as a Sr Principal Design Verification Engineer at Cadence Design Systems, specializing in Tensilica processors. Harish's career also includes significant roles at Huawei Technologies as a Staff Design Verification Engineer, Cisco Systems as a Hardware Engineer, Juniper Networks as an MTS, KPIT Cummins Infosystem Ltd as an Associate Project Lead, and eInfochips Ltd as a Hardware Engineer/Project Lead. Harish has an MSc in Digital Systems (Electronics) from the University of Hertfordshire and multiple engineering degrees in Electronics and Communications from Dharmsinh Desai University and Gujarat University, complemented by studies in Innovation and Entrepreneurship at Stanford University.