J. Swarnkar

J. Swarnkar is an experienced digital design professional currently serving as the Digital Design Lead at Apple since October 2017. Prior to this role, J. Swarnkar worked at Inphi Corporation from September 2012 to September 2017, where responsibilities included leading the chip development for the Vega™ family of low power PAM4 Gearbox and Retimer DSPs, as well as overseeing digital design activities for a 100G Optical Transceiver chip. J. Swarnkar's earlier experience includes a tenure as a Principal Design Engineer at Marvell, focusing on DDR Controller design, and as a Staff Design Engineer at STMicroelectronics, specializing in memory controller design and analysis. Academic qualifications include a Master of Technology in VLSI Design Technology from the Indian Institute of Technology, Delhi, and a Bachelor of Engineering in Computer Engineering from the University of Rajasthan.