Jeff Marker

Jeff Marker is an FPGA/ASIC Engineer with 20 years of experience, including 15 years specializing in RTL/Verilog/VHDL design for FPGAs and ASICs. They have extensive expertise in 802.11 WLAN, DSP algorithms, and Python. Currently, they serve as a Machine Learning HW IP Architect at Apple, focusing on low-power ML inference engine architecture and front-end ASIC design. Previously, they held significant roles at companies such as Ixia, General Dynamics, and Keysight Technologies. Jeff also earned a degree with a GPA of 3.9 and is currently pursuing further education.