Mandar Joshi is a CPU Design Engineer at Apple since November 2025, with prior experience as a Physical Design Engineer at Analog Devices from November 2024 to November 2025. Before that, Mandar led a team at Flex Logix Technologies, Inc. from April 2022 to November 2024, achieving significant improvements in design time for eFPGA accelerator IPs. Mandar's extensive background includes roles at Intel Corporation from January 2014 to April 2022, focusing on subsystem-level timing closure and leading the flow of a multi-instantiated DATA block at the DDR PHY MEM-IP team. Earlier career experiences include positions at Broadcom and internships in Integrated Circuit Design, complemented by teaching roles at San José State University and VES Institute of Technology. Mandar holds a Master of Science in Electrical Engineering from San José State University and a Bachelor of Engineering in Electronics Engineering from VES Institute of Technology.
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