Pavan Badiger

Pavan Badiger is an experienced DFT Engineer with a solid background in digital design and test methodologies, spanning roles at leading technology firms. From June 2011 to July 2012, Pavan worked as a Project Engineer at Wipro Technologies, gaining hands-on experience in DFT processes including synthesis and scan insertion. Subsequently, at SmartPlay Technologies from July 2012 to June 2013, Pavan developed in-house DFT training materials. At Intel Corporation, from June 2015 to March 2020, Pavan achieved significant improvements in ATPG flows and implemented RTL-based DFT checking. Since March 2021, Pavan has been employed as a DFT Engineer at Apple, contributing to validation and test strategy development for various IPs. Pavan also has internship experience at Broadcom, focused on protocol-aware testing and Ethernet IP verification. Pavan holds a Master of Science in Electrical and Electronics Engineering from Arizona State University with a 3.75 GPA and a Bachelor of Engineering in Electronics and Communications from PES Institute of Technology with an 8.72 GPA.