Rajat Sengupta

Rajat Sengupta is a Senior Physical Design and STA Engineer at Apple, where they drive IPC level timing convergence for advanced 3nm and 5nm designs. With 15 years of experience in multi-voltage physical design and full chip timing convergence, Rajat has a strong background in leading timing signoff for various projects. Previously, they worked at Intel as a CPU Design Engineer, contributing to high-speed design for CPU and mentoring partition owners on design convergence. Rajat holds a Master of Science in Electrical Engineering from Arizona State University and a Bachelor of Engineering in Electronics and Communication from Manipal Institute of Technology.