Randa Bernales is a SOC Power and Performance Architect currently at Apple since 2025, having previously held the role of SOC Power Architect at Google from 2021 to 2025. Randa's extensive experience includes serving as a Senior Power and Performance Hardware Engineer at Intel Corporation from 2013 to 2021, where they led power and performance efforts for imaging workloads. Randa's educational background includes a PhD and a Master of Science in Computer Engineering from the University of Louisiana at Lafayette, as well as a B.S. in Electrical Engineering from the University of Balamand. With expertise in VLSI for biomedical applications and low energy delay product circuits, Randa utilizes a diverse skill set that encompasses software and design languages such as Verilog and C++.
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