Sagar Jain has a diverse background in VLSI design and engineering, beginning as a Front End VLSI Design Trainee at CDAC in June 2017. Sagar progressed to roles such as ASIC Design Engineer at NVIDIA, where optimization of operational run-times and development of automated flows for logical and physical netlist conversions were key contributions from July 2019 to August 2022. Following this, Sagar served as a Senior Engineer at SiFive, focusing on the automation of signoff flows for advanced nodes. Additionally, Sagar held a project trainee position at Texas Instruments, designing and verifying a MIPI Slave IP. Currently, Sagar is advancing knowledge and skills as a Physical Design Engineer at Apple and pursuing a Master of Science in Electrical and Computer Engineering at UCLA. Sagar holds a Bachelor of Technology in Electronics and Communications Engineering from Delhi Technological University.
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