Savan Patel

Savan Patel is a skilled engineer with a strong background in electronics and communications. Savan gained valuable experience as a Product Development Engineer Intern at Intel Corporation, where responsibilities included generating vector files and simulating for ATE verification. As an ASIC Physical Design Intern at Intel, Savan managed RTL to GDS-II implementations and engaged in various physical design processes, employing tools such as Synopsys Primetime for block-level static timing analysis. Currently, Savan serves as a Low Power Methodology Engineer at Apple. Previous experience includes a role as a Research And Development Engineer at Hitachi Hi-Rel Power Electronics. Savan holds a Bachelor of Technology in Electronics and Communications Engineering from Dharmsinh Desai University and a Master of Science in Electrical and Electronics Engineering from San Jose State University.