Stephania A.

Stephania A. is an experienced engineer with a strong background in semiconductor technology and hardware design. Notable roles include working as an ASIC Engineering Intern at Marvell Semiconductor and as a SoC Design Verification Engineer at Apple. Previous experience includes a position as an R&D Engineer-Hardware Design at Tejas Networks, where Stephania A. contributed to the design of FPGA-based line cards, and multiple research internships focused on advanced materials and simulation software at institutions such as the National Institute of Technology Calicut and CSIR-CEERI. Proficient in programming languages including C, Shell, and Python, as well as RTL design in Verilog, Stephania A. has developed a solid skill set in both practical engineering and theoretical research.