Vishal Varma is a Senior Manager in Analog Mixed Signal Design with extensive expertise in ASIC and FPGA design and development. Currently leading a team at Apple since 2020, Vishal has previously held significant roles at Sibridge Technologies, PLX Technology, ISRO, and e-Infochips, gaining hands-on experience in architecture definition, RTL coding, and silicon validation across various high-speed designs. Vishal earned a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from C.U. Shah College of Engineering and Technology in 2001.
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