Yahya Khateeb

Yahya Khateeb is an experienced individual contributor and manager in design verification at Apple Inc., specializing in SOC/ASIC verification. With a robust background in architecting object-oriented verification environments, they have held notable positions at Sun Microsystems Inc., PLX Technology Inc., and Synopsys, where they significantly influenced verification practices and methodologies. Yahya's expertise encompasses SystemVerilog, UVM, and a variety of protocols, with a commitment to enhancing development processes through best practices and automation. They earned a BE in Industrial Electronics from Bharati Vidyapeeth and an MS in Electrical and Computer Engineering from Portland State University.