Jeff Schoper

Jeff Schoper is an experienced engineering professional with a robust background in ASIC design and semiconductor physical implementation. Currently serving as an ASIC Design Engineer at Aptina Imaging since July 2007, Jeff specializes in the physical implementation of imaging integrated circuits, utilizing tools such as Cadence Encounter and Sequence Cooltime, along with occasional use of Cadence Virtuoso. Prior experience includes roles as a Semiconductor Physical Implementation Engineer at Micron Technology and a Design Engineer at Agilent Technologies, focusing on backend design, floorplanning, routing, and timing closure for imaging ASICs. Jeff's career began as a Product Engineer at Hewlett Packard, spanning from 1985 to 1999. Jeff holds a Bachelor of Science in Electrical Engineering from the University of Idaho, earned between 1978 and 1982, and is a graduate of Bear Lake High School.