Daniel L. is a seasoned engineer with extensive experience in ASIC and FPGA design. They served as a Senior ASIC Design Engineer at Intel Corp from 1994 to 1998 and held various roles at prominent companies, including Staff Design Engineer at Seagate Technology and Lead Logic Design Engineer at Ciena from 2013 to 2021. Most recently, they have been a Sr. Staff Engineer at Aptiv since 2024 and previously worked as a Principal Comm Architect/Design Engineer at Lattice Semiconductor from 2021 to 2024. Daniel is currently pursuing a BS at the University of California, Davis, and an MS at California State University-Sacramento.
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