Teruo Utsumi

Teruo Utsumi has over 30 years of work experience in the engineering field. Teruo began their career in 1988 as a HW Engineer at Fujitsu Ltd., Japan, where they were responsible for system, board, and chip level design for the VPP vector parallel supercomputer. Teruo then moved to Silicon Graphics in 1997, where they held the roles of Technical Lead Engineer and MTS. In 2009, Utsumi joined Algorithimica as a Design Engineer and Mugen Computing as an FPGA/ASIC Design Consultant, specializing in the high and low level logic optimization and development of applications for FPGA-based accelerators. Teruo then moved to SA Photonics, Inc. in 2020 as a Senior FPGA Engineer, and most recently joined Aril Inc. in 2022 as a Staff Engineer.

Teruo Utsumi attended the University of California, Berkeley from 1983 to 1987, where they earned a Bachelor of Science in Electrical Engineering and Computer Science.