Aditya prasad

Aditya Prasad is a Senior Engineer with extensive experience in the memory subsystem domain, having worked as a Verification Engineer. They held positions at Xilinx, where they specialized in SDRAM memory controller VIP design and gained hands-on experience with advanced protocols such as DDR4 and HBM2e. Currently serving as a Senior DV Engineer at Arm, Aditya is skilled in various tools, including VIVADO and Python, and has a strong foundation in electronics and communication, holding a Bachelor's degree from Sir C R Reddy College of Engineering and a Master's degree from the Indian Institute of Technology, Kanpur.