Bharat Lagali

Bharat Lagali is a VLSI Design Verification Engineer with extensive experience in protocols including PCI Express and 40G Ethernet. Currently serving as a Staff Engineer at Arm, Bharat's expertise encompasses SoC and ASIC verification, formal verification, and design verification tool usage like Synopsys VCS and JasperGold. Previous roles include Technical Lead at eInfochips and Project Lead at Mobiveil Inc., as well as significant positions at HCL Technologies and Analog Devices. Bharat holds a Master’s degree in Microelectronics from the University of Newcastle-upon-Tyne and a Bachelor’s degree in Electrical and Electronics Engineering from Visvesvaraya Technological University.