Bipin Prasad

Bipin Prasad is an experienced professional in CPU design with a strong background in hardware design engineering. Currently employed at Arm since September 2017, Bipin focuses on CPU design. Prior positions include a Senior Hardware Design Engineer role at Arteris, where interconnect design was the primary responsibility, and a Senior Member of Technical Staff at Oracle, where Bipin co-architected a coherency protocol for a multi-core SoC. Experience also includes notable roles at Texas Instruments, where Bipin was a Digital Design Engineer responsible for the Level 1 Instruction Cache Controller on C7x Multicore DSPs, as well as involvement in verification for Level 1 Data Cache, and a Physical Design Engineer role at Fulcrum Microsystems. Educational credentials encompass a Master of Science in Electrical Engineering from the University of Southern California and a Credential of Readiness from Harvard Business School Online.