Florent Laval

Florent Laval is a UVM Engineer with a Master’s degree in Digital Sciences from the Ecole supérieure de Chimie Physique Electronique de Lyon, which they obtained in 2019. With five years of experience in regulated environments, Florent worked at CAHORS as an intern, where they gained insights into production constraints and teamwork. They then contributed to verification and tooling automation at Infineon Technologies, developing a constraint random code generator model and a UVM compliant system Verilog testbench. Between 2020 and 2022, Florent served as an FPGA/UVM verification Engineer at Centum T&S for Framatome, focusing on nuclear environment verification and documentation. Currently, Florent is an Ingénieur vérification at Arm.