Harsh Shah is an experienced engineer with a strong background in embedded systems and verification. Currently serving as a Principal Engineer at Arm since July 2014, Harsh has led projects on next-generation M-class cores and Functional Safety (FuSa) initiatives, building on previous roles as a Staff Engineer and Senior Verification Engineer, where expertise was developed in Cortex M-class microcontrollers. Harsh's career includes significant accomplishments in leading verification projects and working in CPU engineering focused on high-level verification and Functional Safety. Prior experience includes roles at TatvaSoft as an Associate Software Engineer and Nokia Siemens Networks as a BSS trainee engineer. Harsh holds a Master’s Degree in Embedded Systems from Nirma University and a Bachelor's Degree in Electronics and Communication Engineering from Dharmsinh Desai University.
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