Jaydev Vn

Jaydev VN is a seasoned professional in the semiconductor and VLSI industry, currently serving as a Senior Manager at Aatral Technologies India Pvt Ltd since January 2023, and has held a similar position at Capgemini since April 2018, specializing in technical project management and people management. With a strong background in Advanced Mixed Signal (AMS), RF, custom and compiler memory, library development, physical design, and verification, Jaydev VN has also contributed to Azventa Technologies as a Technical Manager, ARM as a Lead Layout Designer, and Intel Corporation as a Memory Layout Design Engineer. Prior experience includes a role as an Analog Mixed Signal Layout Designer at Analog Devices and a VLSI Layout Design Engineer at NetLogic Microsystems. An academic foundation in VLSI Design was established with an MSc Engineering degree from Ramaiah Institute of Technology.