JH Hong is currently a Principal FAE at Arm, specializing in RTL design for mobile SoCs and Verilog simulation for digital design verification. Prior to this role, JH worked as a Sr Principal Application Engineer at Cadence Design Systems from 2019 to 2024 and as a Principal Engineer at Samsung Electronics from 2004 to 2019, focusing on ARM-based system architecture design and digital design in high bandwidth memory. JH holds an education background from Korea University, where they studied from 1999 to 2001.
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