Jnaneswar B

Jnaneswar B is an experienced Technical Manager currently working as a Principal Engineer at Arm in Austin, Texas. They have a demonstrated history in the semiconductors industry, excelling in areas such as EDA, RTL Design, and Universal Verification Methodology (UVM). Jnaneswar holds an M.S. in VLSI CAD from Manipal University and has held various engineering roles, including Design Verification Engineer at Facebook and Senior Technical Manager at Synapse Design. Their past consulting experience includes work with companies like Texas Instruments and Cypress Semiconductor.