Kedhar Malla

Kedhar Malla is a Memory Circuit Design Engineer with seven years of experience specializing in full custom SRAM memory circuits and verification. They have worked with various memory architectures, including pseudo 2-port, single port, two port, and dual port, across technology nodes such as 22nm, 12lp/12lpplus, 5lpe, N4P, and N3E. Kedhar's career includes roles at Arm, where they progressed from Design Engineer to Staff Design Engineer, and prior experience at INVECAS focusing on circuit optimization and statistical analysis. They hold a Bachelor of Technology in Electronics and Communication Engineering and a Master's degree in Microelectronics.