Lovish Masand is a highly experienced Principal Design Engineer at Arm, with a strong background in full chip timing analysis and physical design implementation on advanced sub-10nm technology nodes since April 2020. Previously, Lovish held positions as a Staff Design Engineer at Arm, Sr. Silicon Design Engineer at AMD, and gained valuable experience as a Research and Teaching Assistant at Arizona State University, focusing on random effects measurement test structures. Lovish’s earlier roles include Sr. Application Engineer at Cadence Design Systems and Field Support Engineer at Alcatel-Lucent, complemented by training in electronic design verification at Mentor Graphics. Lovish holds a Master of Science in Electrical Engineering from Arizona State University and a Bachelor's of Technology in Electronics and Telecommunication from Amity Institute of Telecom Tech & Management, along with various certificates from the Indian Institute of Technology, Delhi.
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