Manish Kumar Jain

Manish Kumar Jain is a Principal Engineer at ARM with over 15 years of experience in the field of Physical Design of VLSI. They have been instrumental in 27+ successful full chip tape outs, with expertise in full chip floorplanning and place and route at Qualcomm, as well as hierarchical partitioning at Cadence. Manish previously worked at Wipro Technologies, focusing on the VLSI Physical Design Flow of multi-million gate full chips. They hold a B.Tech in Electronics and Communication Engineering from Vellore Institute of Technology, where they achieved a CGPA of 9.05 out of 10.