Marcin Rodzik

Marcin Rodzik is a skilled verification engineer with expertise in System Verilog, UVM, and SVUnit. Marcin has extensive experience in developing verification environments for various hardware projects, including H.264/AVC and JPEG2000 hardware encoders. They have held positions at companies such as Arm and Cadence Design Systems, advancing from Junior Specialist to Staff Engineer in GPU verification. Marcin holds a B.Sc. and M.Sc. from the Warsaw University of Technology.