Péter Cseh

Péter Cseh is an electrical engineer with experience in FPGA, ASIC, microcontrollers, and signal processing. They have held roles such as FPGA Verification Engineer at Ericsson, FPGA Engineer at Flex, and RTL Design Engineer at AImotive, and they are currently a Senior Engineer at Arm. Péter holds a Bachelor of Science and a Master of Science in Electrical and Electronics Engineering from Óbudai Egyetem and Budapest University of Technology and Economics, respectively. They are particularly interested in RTL design and related technologies, always eager to embrace new challenges in their field.