Raghavendra Reddy Yenumula is a skilled Silicon Validation Engineer with over 7 years of experience in SoC post-silicon validation. Currently working as a Sr Silicon Validation Engineer at Arm, they focus on test methods development and validation. Previously, Raghavendra held roles at Tessolve and Microsoft, where they specialized in ATE test development and debugging using Advantest V93K and Teradyne UltraFlex platforms. Raghavendra's educational background includes a Bachelor of Science in Electronics and two advanced degrees in Microelectronics and Electronics and Instrumentation.
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