Rajeev K is a seasoned SOC Design Engineer with extensive experience in DFT and front-end design and verification of Debug IPs. They worked as a Senior Engineering Consultant at Sondrel Ltd from 2018 to 2021 and served as a VLSI Engineer at Intel Corporation from 2006 to 2017, gaining exposure to various areas of DFT and Post Silicon Enabling. Currently, Rajeev holds the position of Principal Design Engineer at Arm since 2025, following their role as a Senior ASIC Design Engineer at Mentor Graphics from 2021 to 2025. Rajeev completed a Master of Science in Embedded Systems at MIT Manipal and is pursuing a Bachelor of Technology in Electronics and Instrumentation at Cochin University of Science and Technology.
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