Rajesh Kumar

Rajesh Kumar is a seasoned Physical Design Lead with expertise in RTL to GDSII processes, specializing in full chip and block level physical design across various technology nodes, including 12nm to 130nm. They held the position of Soc Design Lead at Intel Corporation from 2018 to 2023, overseeing full chip integration for significant projects. Prior to that, Rajesh worked with notable companies such as Cadence Design Systems and Broadcom, contributing to critical physical design initiatives. Currently, Rajesh serves as a Senior Principal Engineer at Arm, continuing to advance in the field of IC design. Rajesh earned a B.E. in Engineering from Madurai Kamaraj University.