Rajesh S.

Rajesh S. is a Senior Engineer at Arm, focusing on research in architecture to enhance the scalability of computer systems for cloud and machine learning workloads. Prior to this role, Rajesh was a Graduate Researcher at the University of Wisconsin-Madison, working on data reuse mechanisms in HPC and ML workloads within the Heterogeneous Architectures Lab. Additional experience includes serving as a Graduate Teaching Assistant in electrical engineering and computer science courses, a Research Co-op at AMD conducting feasibility studies on sparse linear algebra operators, and a Network on Chip Design Engineer at Qualcomm. Rajesh also possesses extensive experience as a Design Engineer at Analog Devices, contributing to multi-core SoC design, and has held various internship positions related to embedded systems and integrated circuit design. Rajesh earned a Master of Science in Electrical and Computer Engineering from the University of Wisconsin-Madison and a Bachelor of Engineering in Electronics and Communication from PES University.