Rakesh Raman

Rakesh Raman is a highly motivated hardware engineer currently serving as a Staff Engineer at Arm, where they lead verification efforts for SMMU caches and TLB in the CoreLink MMU-700 project. Rakesh previously held the position of Senior Engineer at Arm, contributing to architectural verification and leading a team in dynamic functional verification. With a BE(Hons) in Electronics and Instrumentation from the Birla Institute of Technology and Science, Pilani, and dual Master's degrees in Embedded Computing Systems from Technische Universität Kaiserslautern and Norwegian University of Science and Technology, Rakesh has built a solid foundation in complex design solutions and verification challenges. Additional experience includes roles at ST-Ericsson, Cambridge Silicon Radio, and Freescale Semiconductor.