Romany Grais

Romany Grais is a Staff CPU Physical Implementation Engineer at Arm, where they focus on physical design from RTL to GDSII. They previously held the position of Senior Digital Implementation Engineer at Arm, contributing to the physical implementation of test chips and CPU cores. Before this, Romany worked as an ASIC Physical Design Engineer at Synopsys, where they developed methodologies for automating digital implementations for SERDES IPs. Romany earned a Bachelor of Science in Electronics and Communications Engineering and a Master of Science in Electronics Engineering from Cairo University, achieving a GPA of 3.7/4.0 in the latter.