Rupesh Bartunia

Rupesh Bartunia has extensive experience in hardware engineering and ASIC design, highlighted by significant roles at major technology companies. From November 2008 to May 2017, Rupesh worked at Cisco as a Hardware Engineer, specializing in Networking ASICs including VOQs and high bandwidth L2/L3 layer rewrite accelerators. Prior to Cisco, Rupesh served as an ASIC Design Engineer at RF Silicon, focusing on IP development for AMBA-based Baseband SoCs, and held a position as Senior Design Engineer at Tata Elxsi, concentrating on board design and FPGA prototyping. More recently, Rupesh has been with Intel Corporation since September 2019, working on SoC microarchitecture and leading FEBE efforts, with a transition to Arm as a Principal Design Engineer in February 2025. Educational qualifications include a Bachelor of Engineering in Electronics and Telecommunication from Shri G S Institute of Technology & Science and a Master of Technology in Electronics Design and Technology from the Indian Institute of Science.