Rutuja Patil

Rutuja Patil is a Design Verification Engineer at Arm, with previous experience as a SoC Design Engineer and intern at Intel Corporation. At Intel, Rutuja launched and debugged regression tests for IP verification, developed Python scripts for automation, and conducted synthesis and lint checks on hard IP. Additionally, Rutuja tested and debugged FPGA GUI and worked on the development of a UVM environment for IP. Rutuja held positions as an Engineering Student Ambassador and Laboratory Assistant at Portland State University, and developed an application for fire panel control during an internship at Johnson Controls. Rutuja holds a Master of Science in Electrical, Electronics and Communications Engineering from Portland State University and a Bachelor of Engineering in Electronics and Telecommunication from Cummins College of Engineering for Women.