Ryan Lim is a highly experienced engineer with a robust background in system architecture and design. Currently serving as a System Architect & Distinguished Engineer at Arm since February 2009, Ryan Lim has previously held the role of Senior Principal IoT Architect. Prior experience includes positions as Chief Design Engineer at ARC, where significant contributions were made to the ARC700 core architecture, and as Senior Design Engineer at Siroyan, where oversight of the memory sub-system for DSP micro-architecture was provided. Additional experience as a Design Engineer at Philips Semiconductors involved collaborating with IP providers and analyzing system architecture. Ryan Lim holds a PhD in Digital NeuroMorphic Systems and a BEng (Hons) in Electronics & Electrical Engineering from Loughborough University.
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