Sameer Agrawal

Sameer Agrawal is an experienced semiconductor professional specializing in design and product development in CMOS and FinFET processes down to 3nm. They have led significant projects, including the world's largest 8Mb L1 Cache development in 40nm, and have accrued extensive knowledge in analog and digital design, as well as SRAM design. Sameer has held senior positions at companies such as Intel, Virage Logic, and Synopsys, and currently focuses on design reliability and quality at Arm. They hold a B.Tech in Electrical Engineering from the Indian Institute of Technology, Kanpur.