Sreeram Jayadev

Sreeram Jayadev is a Solutions Architect at ARM, specializing in ASIC and RTL Development with extensive experience in hardware description languages such as Verilog, System Verilog, and VHDL. They have previously held positions at Qualcomm, where they developed a scalable debug and trace infrastructure for Snapdragon chipsets, and Intel Corporation, where they led microarchitecture and design for a multi-clock domain Fuse controller. Sreeram's academic background includes a Master’s in Electrical Engineering from North Carolina State University and a Bachelor’s in Electronics and Communications Engineering from the University of Madras. Their professional expertise encompasses block design, verification methodologies, and static timing analysis.