Stéphane Forey

Stéphane Forey is a seasoned hardware design engineer with extensive experience in the field, currently serving as a Staff Hardware Design Engineer in the GPU Group at ARM since March 2012, focusing on next-generation Mali GPUs. Prior roles include Senior DSP & FPGA Design Engineer at COM DEV, which involved VHDL design and DSP algorithm design for aerospace communications systems, and ASIC Engineer at ARC International, where responsibilities encompassed Verilog design and product release maintenance for ultra-low power CPUs. Previous positions include FPGA Design Engineer at Fujitsu Telecommunications Europe Limited, ASIC Engineer at Philips Applied Technologies, and various consulting roles at Altran, Parrot, AREVA T&D, GlobespanVirata, and T.SQWARE, honing skills in VHDL, FPGA, and ASIC design and verification. Stéphane Forey holds a DUT in GEII from Université Paris 13 and graduated from ENIB.